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Data Sheet No. PD60238 revE
IRS2153(1)D(S)PbF
SELF-OSCILLATING HALF-BRIDGE DRIVER IC
Features
Integrated 600 V half-bridge gate driver CT, RT programmable oscillator 15.4 V Zener clamp on VCC Micropower startup Non-latched shutdown on CT pin (1/6th VCC) Internal bootstrap FET Excellent latch immunity on all inputs and outputs +/- 50 V/ns dV/dt immunity ESD protection on all pins 8-lead SOIC or PDIP package Internal deadtime
Product Summary
VOFFSET Duty cycle Driver source/sink current Vclamp Deadtime 600 V Max 50% 180 mA/260 mA typ. 15.4 V typ. 1.1 s typ. (IRS2153D) 0.6 s typ. (IRS21531D)
Description
The IRS2153(1)D is based on the popular IR2153 selfoscillating half-bridge gate driver IC using a more advanced silicon platform, and incorporates a high voltage half-bridge gate driver with a front end oscillator similar to the industry standard CMOS 555 timer. HVIC and latch immune CMOS technologies enable rugged monolithic construction. The output driver features a high pulse current buffer stage designed for minimum driver cross-conduction. Noise immunity is achieved with low di/dt peak of the gate drivers.
Package
PDIP8 IRS2153(1)DPbF
SO8 IRS2153(1)DSPbF
Typical Connection Diagram
+ AC Rectified Line
RVCC
VCC
1
8
VB CBOOT MHS
IRS2153(1)D
RT
2
7
HO
RT CT CVCC CT COM
3
6
VS
L
RL
4
5
LO
MLS
- AC Rectified Line
1
IRS2153(1)D
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.
Symbol
VB VS VHO VLO IRT VRT VCT ICC IOMAX dVS/dt PD PD RthJA RthJA TJ TS TL
Parameter Definition
High side floating supply voltage High side floating supply offset voltage High side floating output voltage Low side output voltage RT pin current RT pin voltage CT pin voltage Supply current (Note 1) Maximum allowable current at LO and HO due to external power transistor Miller effect. Allowable offset voltage slew rate Maximum power dissipation @ TA +25 C, 8-Pin DIP Maximum power dissipation @ TA +25 C, 8-Pin SOIC Thermal resistance, junction to ambient, 8-Pin DIP Thermal resistance, junction to ambient, 8-Pin SOIC Junction temperature Storage temperature Lead temperature (soldering, 10 seconds)
Min.
-0.3 VB - 25 VS - 0.3 -0.3 -5 -0.3 -0.3 ---500 -50 ---------55 -55 ---
Max.
625 VB + 0.3 VB + 0.3 VCC + 0.3 5 VCC + 0.3 VCC + 0.3 20 500 50 1.0 0.625 85 128 150 150 300
Units
V
mA V mA V/ns W C/W
C
Note 1: This IC contains a zener clamp structure between the chip VCC and COM which has a nominal breakdown voltage of 15.4 V. Please note that this supply pin should not be driven by a DC, low impedance power source greater than the VCLAMP specified in the Electrical Characteristics section.
2
IRS2153(1)D
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions.
Symbol
VBS VS VCC ICC TJ
Parameter Definition
High side floating supply voltage Steady state side floating supply offset voltage Supply voltage Supply current Junction temperature
Min.
VCC - 0.7 -3.0 (Note 2) VCCUV+ +0.1 V (Note 3) -40
Max.
VCLAMP 600 VCC CLAMP 5 125
Units
V mA C
Note 2: It is recommended to avoid output switching conditions where the negative-going spikes at the VS node would decrease VS below ground by more than -5 V. Note 3: Enough current should be supplied to the VCC pin of the IC to keep the internal 15.6 V zener diode clamping the voltage at this pin.
Recommended Component Values
Symbol
RT CT
Parameter Component
Timing resistor value CT pin capacitor value
Min.
1 330
Max.
-----
Units
k pF
VBIAS (VCC, VBS) = 14 V, VS=0 V and TA = 25 C, CLO = CHO = 1 nF.
Frequency vs. RT
1,000,000 CT Values 100,000 Frequency (Hz) 10,000 1,000 100 10 1,000 330pf 470pF 1nF 2.2nF 4.7nF 10nF
10,000
100,000
1,000,000
RT (Ohm)
For further information, see Fig. 12. 3
IRS2153(1)D
Electrical Characteristics
VBIAS (VCC, VBS) = 14 V, CT = 1 nF, VS=0 V and TA = 25 C unless otherwise specified. The output voltage and current (VO and IO) parameters are referenced to COM and are applicable to the respective output leads: HO or LO. CLO = CHO = 1 nF.
Symbol
VCCUV+ VCCUVVCCUVHYS IQCCUV IQCC ICC VCC CLAMP IQBS VBSUV+ VBSUVILK
Definition
Rising VCC undervoltage lockout threshold Falling VCC undervoltage lockout threshold VCC undervoltage lockout hysteresis Micropower startup VCC supply current Quiescent VCC supply current VCC supply current VCC zener clamp voltage Quiescent VBS supply current VBS supply undervoltage positive going threshold VBS supply undervoltage negative going threshold Offset supply leakage current
Min
10.0 8.0 1.6 ------14.4 --8.0 7.0 --18.4 88 ----0.20 ----2.2 -------------
Typ
11.0 9.0 2.0 130 800 1.8 15.4 60 9.0 8.0 --19.0 93 50
0.02
Max
12.0 10.0 2.4 170 1000 --16.8 80 9.5
Units
Test Conditions
Low Voltage Supply Characteristics V VCC VCCUVRT = 36.9 k ICC = 5 mA
A mA V A
Floating Supply Characteristics
V 9.0 50 19.6 100 --1.0 0.6 ----2.4 50 300 50 300 100 50 300 mV IRT = -100 A IRT = -1 mA IRT = 100 A IRT = 1 mA VCC VCCUVIRT = -100 A,
VCT = 0 V
A
VB = VS = 600 V RT = 36.5 k RT = 7.15 k
fo < 100 kHz VCC = 7 V
Oscillator I/O Characteristics fOSC d ICT ICTUV VCT+ VCTVCTSD VRT+ VRTVRTUV Oscillator frequency RT pin duty cycle CT pin current UV-mode CT pin pulldown current Upper CT ramp voltage threshold Lower CT ramp voltage threshold CT voltage shutdown threshold High-level RT output voltage, VCC - VRT Low-level RT output voltage UV-mode RT output voltage kHz % A mA V
0.30 9.32 4.66 2.3 10 100 10 100 0 10 100
VRTSD
SD-mode RT output voltage, VCC - VRT ---
IRT = -1 mA,
VCT = 0 V
4
IRS2153(1)D
Electrical Characteristics
VBIAS (VCC, VBS) = 14 V, CT = 1 nF, VS=0 V and TA = 25 C unless otherwise specified. The output voltage and current (VO and IO) parameters are referenced to COM and are applicable to the respective output leads: HO or LO. CLO = CHO = 1 nF.
Symbol
VOH VOL VOL_UV tr tf tsd td td IO+ IO-
Definition
High-level output voltage Low-level output voltage UV-mode output voltage Output rise time Output fall time Shutdown propagation delay Output deadtime (HO or LO) (IRS2153D) Output deadtime (HO or LO) (IRS21531D) Output source current Output sink current
Min
------------0.65 0.35 -----
Typ
VCC COM COM 120 50 350 1.1 0.6 180 260
Max
------220 80 --1.75 0.85 -----
Units
Test Conditions
Gate Driver Output Characteristics IO = 0 A V IO = 0 A, VCC VCCUVns
s s mA
Bootstrap FET Characteristics VB_ON IB_CAP IB_10V VB when the bootstrap FET is on VB source current when FET is on VB source current when FET is on --40 10 13.7 55 12 ------V mA
CBS=0.1 uF VB=10 V
5
IRS2153(1)D
Lead Definitions
VCC
1
8
VB
IRS2153(1)D
RT
2
7
HO
CT
3
6
VS
COM
4
5
LO
Symbol
VCC RT CT COM LO VS HO VB Oscillator timing resistor input Oscillator timing capacitor input IC power and signal ground Low-side gate driver output High voltage floating supply return High-side gate driver output High side gate driver floating supply
Lead Description
Logic and internal gate drive supply voltage
6
IRS2153(1)D
Functional Block Diagram
RT 2 R + R R + R/2 SQ R1 R2 S Q Q
DEAD TIME DEAD TIME PULSE
HV LEVEL SHIFT
8
VB
Q PULSE FILTER R S
6
BOOTSTRAP DRIVE
7
HO
VS
GEN
15.4V
1 VCC
CT 3 R/2
+ -
DELAY
5
LO
4
COM
M1
UV DETECT
7
IRS2153(1)D
Timing Diagram
Operating Mode
VCCUV+
VCC
Fault Mode: CT <1/6*VCC
2/3 VCC
VCT
1/3 VCC 1/6 VCC
VCC
LO
VCC
DT
HO
DT
VCC
VRT
IRT
Switching Time Waveform
Deadtime Waveform
90%
tr 90%
tf
LO
DTLO
10%
DTHO
HO
90%
HO LO
10%
10%
8
IRS2153(1)D
Functional Description
Under-voltage Lock-Out Mode (UVLO)
The under-voltage lockout mode (UVLO) is defined as the state the IC is in when VCC is below the turn-on threshold of the IC. The IRS2153(1)D under voltage lock-out is designed to maintain an ultra low supply current of less than 170 A, and to guarantee the IC is fully functional before the high and low side output drivers are activated. During under voltage lock-out mode, the high and low-side driver outputs HO and LO are both low.
Bootstrap MOSFET
The internal bootstrap FET and supply capacitor (CBOOT) comprise the supply voltage for the high side driver circuitry. The internal boostrap FET only turns on when LO is high. To guarantee that the high-side supply is charged up before the first pulse on pin HO, the first pulse from the output drivers comes from the LO pin.
Normal operating mode
Once the VCCUV+ threshold is passed, the MOSFET M1 opens, RT increases to approximately VCC (VCC-VRT+) and the external CT capacitor starts charging. Once the CT voltage reaches VCT(about 1/3 of VCC), established by an internal resistor ladder, LO turns on with a delay equivalent to the deadtime (td). Once the CT voltage reaches VCT+ (approximately 2/3 of VCC), LO goes low, RT goes down to approximately ground (VRT-), the CT capacitor discharges and the deadtime circuit is activated. At the end of the deadtime, HO goes high. Once the CT voltage reaches VCT-, HO goes low, RT goes high again, the deadtime is activated. At the end of the deadtime, LO goes high and the cycle starts over again. The following equation provides the oscillator frequency:
Supply voltage
+ AC Rectified Line RVCC
VCC
1
8
VB CBOOT MHS
RT
IRS2153(1)D
2
7
HO
RT CT CVCC CT COM
3
6
VS
L
RL
4
5
LO
MLS
f~
1 1.453 x RT x CT
- AC Rectified Line
Fig. 1 Typical Connection Diagram Fig. 1 shows an example of supply voltage. The start-up capacitor (CVCC) is charged by current through supply resistor (RVCC) minus the start-up current drawn by the IC. This resistor is chosen to provide sufficient current to supply the IRS2153(1)D from the DC bus. CVCC should be large enough to hold the voltage at Vcc above the UVLO threshold for one half cycle of the line voltage as it will only be charged at the peak, typically 0.1 uF. It will be necessary for RVCC to dissipate around 1 W. The use of a two diode charge pump made of DC1, DC2 and CVS (Fig. 2) from the half bridge (VS) is also possible however the above approach is simplest and the dissipation in RVCC should not be unacceptably high.
+ AC Rectified Line
This equation can vary slightly from actual measurements due to internal comparator over- and under-shoot delays. For a more accurate determination of the output frequency, the frequency characteristic curves should be used (RT vs. Frequency, page 3).
Shut-down
If CT is pulled down below VCTSD (approximately 1/6 of VCC) by an external circuit, CT doesn't charge up and oscillation stops. LO is held low and the bootstrap FET is off. Oscillation will resume once CT is able to charge up again to VCT-.
RVCC
VCC
1
8
VB CBOOT MHS DC2 VS CVS L
RT
IRS2153(1)D
2
7
HO
RT CT CVCC CT COM
3
6
RL
4
5
LO
MLS DC1
- AC Rectified Line
Fig. 2 Charge pump circuit The supply resistor (RVCC) must be selected such that enough supply current is available over all operating conditions. Once the capacitor voltage on VCC reaches the start-up threshold VCCUV+, the IC turns on and HO and LO begin to oscillate.
9
IRS2153(1)D
19
100 98 Frequency (kHz) 96 94 92
18.8 Frequency (kHz)
18.6
18.4
18.2
18 11 12 13 VCC(V) 14 15 16
90 -25
0
25
50
75
100
125
Temperature(C)
FREQ vs VCC
FREQ vs TEMP
Fig. 3
1.4
Fig. 4
1.25 1.15 1.05 0.95 0.85 0.75 -25
1.3 1.2
DT(uS)
1.1 1
0.9 11 12 13 VCC(V) 14 15 16
DT(uS)
0
25
50
75
100
125
Temperature(C)
DT vs VCC
DT vs TEMP
Fig. 6 (IRS2153D)
17
Fig. 5 (IRS2153D)
90 80 70 Temperature(C) 60 50 40 30 20 10 0 20 70 120 Frequency(kHz)
15 -25 0 25 50 75 100 125
VCC (V)
16
Temperature (C) VCC CLAMP vs TEMP
Tj vs. Frequency (SOIC)
Fig. 7
Fig. 8
10
IRS2153(1)D
300 250 HOCurrent (mA) 200 150 100 50 0 -25 300
IsinkHO
LO Current (mA)
250 200 150 100 50 0 -25
IsinkLO
IsourceHO
IsourceLO
0
25
50
75
100
125
0
25
50
75
100
125
Temperature(C)
Temperature(C)
IsourceHO,IsinkHO vs Temp
Fig. 9
80 70 IB_CAP, IBS_10V (mA) 60 50 40 30 20 10 0 -25 IBS_10V IB_CAP
IsourceLO,IsinkLO vs Temp
Fig. 10
VOH_HO vs. Frequency
With External BS diode
No external BS diode
16 14 12
VOH_HO (V)
75 100 125
10 8 6 4 2 0 0 50 100 150 200 250 300 350 400
0
25
50
Temperature(C)
IBCAP, IBS10V vs TEMP
T=25C, VS=0V, CHO = 1nF
Frequency (kHz)
Fig. 11
Fig. 12
VOH_HO vs . Fre que ncy vs . Te m p VCC=14V, CHO=1nF, VS=0V 14 12
V H H (V O_O )
10 8 6 4 2 0
hz 6K .4 1 K 20 K 50 K 75 0K 10 5K 12 0K 15 0K 20
Fre que ncy (k Hz)
T=-25c
T=25c
T=75c
T=125c
Fig. 13
11
IRS2153(1)D
IRS2153(1)DPbF
IRS2153(1)DSPbF
12
IRS2153(1)D
LOADED TAPE FEED DIRECTION
B
A
H
D F C
NOTE : CONTROLLING DIM ENSION IN M M
E G
CARRIER TAPE DIMENSION FOR Metric Code Min Max A 7.90 8.10 B 3.90 4.10 C 11.70 12.30 D 5.45 5.55 E 6.30 6.50 F 5.10 5.30 G 1.50 n/a H 1.50 1.60
8SOICN Imperial Min Max 0.311 0.318 0.153 0.161 0.46 0.484 0.214 0.218 0.248 0.255 0.200 0.208 0.059 n/a 0.059 0.062
F
D C E B A
G
H
REEL DIMENSIONS FOR 8SOICN Metric Code Min Max A 329.60 330.25 B 20.95 21.45 C 12.80 13.20 D 1.95 2.45 E 98.00 102.00 F n/a 18.40 G 14.50 17.10 H 12.40 14.40
Imperial Min Max 12.976 13.001 0.824 0.844 0.503 0.519 0.767 0.096 3.858 4.015 n/a 0.724 0.570 0.673 0.488 0.566
13
IRS2153(1)D
PART MARKING INFORMATION
ORDER INFORMATION
8-Lead PDIP IRS2153DPbF 8-Lead PDIP IRS21531DPbF 8-Lead SOIC IRS2153DSPbF 8-Lead SOIC IRS21531DSPbF 8-Lead SOIC Tape & Reel IRS2153DSTRPbF 8-Lead SOIC Tape & Reel IRS21531DSTRPbF
The SOIC-8 is MSL2 qualified. This product has been designed and qualified for the industrial level. Qualification standards can be found at www.irf.com IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105 Data and specifications subject to change without notice. 6/27/2006
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